由電子科學與工程學院主辦的“電子論壇”第89期邀請到臺灣清華大學張廖貴術（Kuei-Shu Chang-Liao）教授，與我校師生共同探討傳統3D Flash Memory中Poly-Si Channel通道、GAA配置、堆疊缺陷層等工藝帶來的問題以及通過界質層的工程來實現高性能的3D Flash Memory的研究工作。具體安排如下，歡迎感興趣的師生參加。
主 題：High Performance 3D Flash Memory Devices with Dielectric Engineering
主講人：張廖貴術（Kuei-Shu Chang-Liao）National Tsing Hua University, TAIWAN
? Polycrystalline silicon (Poly-Si) channel has been widely applied on flash devices for threedimensional(3D) memory integration. Recently, gate-all-around (GAA) configuration was applied on charge-trapping (CT) flash devices, indicating that operation characteristics can be improved by GAA configuration. Furthermore, stacked trapping layer such as Si3N4/high-k was reported to enhance the operation characteristics of CT flash devices. However, thermal budget of fabrication process should be reduced and carefully controlled in 3D flash devices. Therefore, low temperature (LT) formed SiO2 tunneling layer and stacked Si3N4/HfO2 trapping ones on operation characteristics of CT flash device with GAA and Ω-gate nanowire (NW) configurations were comprehensively studied. A faster operation speed and a larger memory window are achieved by GAA configuration. However, the reliability characteristics such as retention and endurance of GAA JL CT flash devices formed with LT processes are worse than those with HT ones. The worse step coverage of dielectrics deposited with LT processes around the channel needs solution to improve the retention characteristics of GAA JL CT flash devices.
Kuei-Shu Chang-Liao received the B.S. and M.S. degrees in Telecommunication and Electronics from National Chiao Tung University, 1984 and 1989, respectively, and the Ph.D. degree in Electrical Engineering from Taiwan University in 1992.
In 1992, Dr. Chang-Liao joined the faculty at Tsing Hua University where he has been a Professor of Department of Engineering and System Science since 1999. In 2000, he was a visiting research fellow at the Department of Electrical Engineering of Yale University, where he was involved in Flash memory and charge pumping measurement. During 2007-2010, he served as the Associate Chairman of Department of Engineering and System Science. His current research interests include high-k/metal gate stack processes in FinFET, Ge or SiGe MOS devices, charge-trapping flash memory devices, and trap analysis in MOS device by charge pumping measurement.
Dr. Chang-Liao is a Distinguished Lecture of IEEE EDS, senior member of IEEE, and member of the Electrochemical Society. He served as the Editor of IEEE Electron Device Letters during 2012-15. He received the excellent Industry-Academic Research Award from Ministry of Education in 2003. He has published over 300 papers in prestigious journals and conferences. He has chaired and served as committeemembers in several international conferences.
編輯：羅莎 / 審核：羅莎 / 發布者：陳偉